1. Field of the Invention
The present invention relates to a method for producing a semiconductor device, and more particularly, to a method for directly connecting an electrode and an impurity-diffused layer formed on a semiconductor substrate.
2. Description of the Related Art
A memory cell circuit to be used for a Static Random Access Memory (SRAM), one of the memory devices is formed from a plurality of Metal Oxide Semiconductor (MOS) transistors. A gate electrode of one of the MOS transistors is electrically connected to an impurity-diffused layer of another MOS transistor adjacent thereto. FIG. 5 is a plan view showing part of an exemplary memory cell circuit with such a configuration. As shown in FIG. 5, a transistor has a gate electrode 300, and a transistor adjacent thereto has an impurity-diffused layer 100. The surface of the impurity-diffused layer 100 is covered with an insulating film, and thus the impurity-diffused layer 100 is directly connected to the gate electrode 300 through an opening 200.
A conventional method for producing a semiconductor device in which the gate electrode 300 is electrically connected to the impurity-diffused layer 100 will be described below referring to FIGS. 3A through 3C.
First, as shown in FIG. 3A, an oxide film for isolation 103 is formed in the surface region of a semiconductor substrate 101, and a gate insulating film 102 is formed on the surface of the semiconductor substrate 101. Next, the gate insulating film 102 is partially etched, and an opening 200 is formed in the gate insulating film 102. A polysilicon film 107 doped with phosphorus is formed so as to cover the surface of the semiconductor substrate 101. The polysilicon film 107 may be replaced with a composite film made of a polysilicon film and a metal silicide film. Then, a resist 108 is formed on the polysilicon film 107 using lithography technique so as to define a gate electrode pattern. A region D is defined between an end portion 108a of the resist 108 and an end portion 102a of the gate insulating film 102 in the semiconductor substrate 101. That is to say, neither the resist 108 nor the gate insulating film 102 are formed above the region D.
Next, as shown in FIG. 3B, the polysilicon film 107 is partially etched using the resist 108 as a mask so as to form a gate electrode 300. At the same time, the region D of the semiconductor substrate 101 is also etched, and a groove 120 is formed in the semiconductor substrate 101. Subsequently, as shown in FIG. 3C, the resist 108 is removed, and then side-walls 121 and 122 made of silicon dioxide are formed on sides of the groove 120. The sidewall 121 is formed also on a side 300a of the gate electrode 300. Arsenic ions are implanted into the semiconductor substrate 101 through the gate insulating film 102 using the gate electrode 300 and the sidewalls 121 and 122 as masks. Thereafter, the semiconductor substrate 101 is annealed. The phosphorus is diffused from the gate electrode 300 to the semiconductor substrate 101, thereby forming an impurity-rich layer 111. The implanted arsenic is activated, thereby forming an impurity-rich layer 112. The impurity-rich layers 111 and 112 are formed so as to be electrically connected to each other, thereby constituting an impurity-diffused layer 100.
However, according to the conventional method, neither the resist 108 nor the gate insulating film 102 are formed above the region D as shown in FIG. 3A. Therefore, when the gate electrode 300 is formed, the region D of the semiconductor substrate 101 is etched, and the groove 120 is formed in the semiconductor substrate 101. When the sidewall 121 is formed on the side 300a of the gate electrode 300 and on the side of the groove 120, the sidewall 122 is also formed on the side of the groove 120. As a result, when the arsenic ions are implanted into the semiconductor substrate 101, the arsenic ions cannot be implanted into a portion of the semiconductor substrate 101 underlying the groove 120 due to the use of the side-walls 121 and 122 as the masks. As a result, at the region D of the semiconductor substrate 101 underlying the groove 120, the impurity-rich layers 111 and 112 cannot be electrically connected to each other. Thus, there is a possibility that the gate electrode 300 and the impurity-rich layer 112 will not be electrically conducted to each other.
Another conventional method for producing a semiconductor device in which the region D is not formed will be described below referring to FIGS. 4A through 4C.
First, as shown in FIG. 4A, an oxide film for isolation 103 is formed in the surface region of a semiconductor substrate 101, and a gate insulating film 102 is formed on the surface of the semiconductor substrate 101. Next, the gate insulating film 102 is partially etched, and an opening 200 is formed in the gate insulating film 102. A polysilicon film 107 doped with phosphorus is formed so as to cover the surface of the semiconductor substrate 101. The polysilicon film 107 may be replaced with a composite film made of a polysilicon film and a metal silicide film. Then, a resist 108 is formed on the polysilicon film 107 using lithography technique so as to define a gate electrode pattern. Both of the resist 108 and the gate insulating film 102 are formed above a region E of the semiconductor substrate 101.
Next, as shown in FIG. 4B, the polysilicon film 107 is partially etched using the resist 108 as a mask so as to form a gate electrode 300. Subsequently, as shown in FIG. 4C, the resist 108 is removed, and then a sidewall 121 made of silicon dioxide is formed on a side 300a of the gate electrode 300. Arsenic ions are implanted into the semiconductor substrate 101 through the gate insulating film 102 using the gate electrode 300 and the sidewall 121 as masks. Thereafter, the semiconductor substrate 101 is annealed. The phosphorus is diffused from the gate electrode 300 to the semiconductor substrate 101, thereby forming an impurity-rich layer 111. The implanted arsenic is activated, thereby forming an impurity-rich layer 112 The impurity-rich layers 111 and 112 are formed so as to be electrically connected to each other, thereby constituting an impurity-diffused layer 100.
According to the above method, considering the registration error, the gate electrode 300 is partially superimposed on the gate insulating film 102 above the region E. Therefore, the semiconductor substrate 101 would not be etched, so that a groove such as the groove 120 described above is not formed when the gate electrode 300 is formed.
However, when the arsenic ions are implanted into the semiconductor substrate 101 through the gate insulating film 102, the arsenic ions cannot be implanted into the region E of the semiconductor substrate 101 due to the use of the gate electrode 300 and the sidewall 121 as the masks. Moreover, in the case where the semiconductor substrate 101 is annealed, the doped phosphorus cannot be diffused to the region E of the semiconductor substrate 101 due to the presence of the gate insulating film 102. Therefore, the region E does not include impurities. As a result, at the region E of the semiconductor substrate 101, the impurity-rich layers 111 and 112 cannot be electrically connected to each other. Thus, there is a possibility that the gate electrode 300 and the impurity-rich layer 112 will not be electrically conducted to each other.
In order to overcome the above problem, it is possible to employ annealing conditions under which the phosphorus and arsenic ions may be easily diffused in the semiconductor substrate 101. When the annealing conditions are employed, the phosphorus and arsenic ions can be further diffused in the semiconductor substrate 101. Thus, the areas of the impurity-rich layers 111 and 112 can be enlarged enough to ensure the electrical conduction between the impurity-rich layers 111 and 112 at the region D (FIG. 3A) or the region E (FIG. 4A). However, this leads to an enlarged impurity-diffused layer including a source region and a drain region. Thus, the use of such annealing conditions would have a disadvantage in that devices constituting a memory circuit become large.